1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the invention relates to a power semiconductor device.
2. Description of the Related Art
A well-known power semiconductor device is a double-diffused metal oxide semiconductor (DMOS) transistor. The DMOS transistor is a MOS field-effect transistor for which a source layer and a channel-forming body layer are formed by double diffusion. The DMOS transistor has a wide range of applications including power supply circuits and driver circuits.
Among the DMOS transistors are laterally diffused (LD) MOS transistors which conduct currents laterally. An LDMOS transistor is structured as follows. For example, it is provided with an N-type epitaxial layer, and a P-type body layer is formed in the surface of the epitaxial layer. An N-type source layer is formed in superposition on the body layer, and a gate insulator (gate insulating film) is formed in a ring shape surrounding the source layer. A ring-shaped gate electrode is formed on an exposed part of the body layer without the source layer being formed therein, with the gate insulator interposed therebetween. An N-type drain layer is formed in the surface of the epitaxial layer in a position opposite to the source layer. A part of the body layer between the source layer and the drain layer forms a channel region.
A characteristic desired of such a DMOS transistor is a high breakdown voltage. A technology for raising the breakdown voltage is known where an offset region between a body layer and a drift layer constituting a part of the drain layer in a gate-length direction is formed and an offset region oxidized layer is formed on an offset region.
Under the foregoing circumstances, the inventors had come to recognize problems as described below. In a DMOS transistor having the above-described structure, the concentration of an impurity tends to increase at an end in a gate-width direction thereof, which brings about a convergence of electric field there. As a result, the high breakdown voltage characteristic can decline at an end in the gate-width direction. Also, in a DMOS transistor of the above-described structure, there exists an interface between a P-type body layer and an N-type epitaxial layer or drift layer below the end in the gate-width direction of the gate electrode. Hence, with a high voltage applied to the drain layer, the electric field intensity rises in a P-N junction below the gate electrode if there is an increase in the aforementioned impurity concentration at the end in the gate-width direction. This condition may cause a current to flow in the region at the end in the gate-width direction when the transistor is off. And the result will be the loss of desired high breakdown voltage characteristic. Thus the reduced high breakdown voltage characteristics at the end in the gate-width direction will limit the high breakdown voltage characteristic of the DMOS transistor.